发明授权
US07660377B2 Device for estimating a timing correction loop error for a digital demodulator 有权
用于估计数字解调器的定时校正回路误差的装置

  • 专利标题: Device for estimating a timing correction loop error for a digital demodulator
  • 专利标题(中): 用于估计数字解调器的定时校正回路误差的装置
  • 申请号: US11270388
    申请日: 2005-11-09
  • 公开(公告)号: US07660377B2
    公开(公告)日: 2010-02-09
  • 发明人: Jacques Meyer
  • 申请人: Jacques Meyer
  • 申请人地址: FR Montrouge
  • 专利权人: STMicroelectronics S.A.
  • 当前专利权人: STMicroelectronics S.A.
  • 当前专利权人地址: FR Montrouge
  • 代理机构: Wolf, Greenfield & Sacks, P.C.
  • 代理商 Lisa K. Jorgenson; William R. McClellan
  • 优先权: FR0452576 20041109
  • 主分类号: H04L7/00
  • IPC分类号: H04L7/00
Device for estimating a timing correction loop error for a digital demodulator
摘要:
A device for providing a digital error signal, for a timing correction loop of a digital demodulator for digital transmission by phase modulation or amplitude and phase modulation, the device successively receiving pairs of digital signals representative of the components of complex signals, and having circuitry for providing a difference signal representative of the difference between the modulus of the complex signal corresponding to the last received pair of digital signals and the modulus of the complex signal corresponding to the previously-received pair of digital signals; circuitry for providing a weighting factor which depends on the angle between the complex signal corresponding to the last received pair of digital signals and the complex signal corresponding to the previously-received pair of digital signals; and circuitry for providing the error signal proportional to the product of the difference signal and of the weighting factor.
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