Invention Grant
- Patent Title: Cache leakage shut-off mechanism
- Patent Title (中): 缓存泄漏关闭机制
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Application No.: US11174204Application Date: 2005-06-30
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Publication No.: US07657767B2Publication Date: 2010-02-02
- Inventor: Stefan Rusu , Tsung-Yung Chang , Kevin Zhang , Fatih Hamzaoglu , Jonathan Shoemaker , Ming Huang
- Applicant: Stefan Rusu , Tsung-Yung Chang , Kevin Zhang , Fatih Hamzaoglu , Jonathan Shoemaker , Ming Huang
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: G06F1/00
- IPC: G06F1/00 ; G06F1/32

Abstract:
In one embodiment of the present invention, a technique is provided to control leakage of a cache sub-array. Other embodiments are disclosed herein. A sleep and shut-off circuit is connected between a virtual supply terminal and a first physical supply terminal to reduce leakage from the cache sub-array when the cache sub-array is disabled in a shut-off mode. The cache sub-array is connected between the virtual supply terminal and a second physical supply terminal. An active circuit is connected to the sleep and shut-off circuit in parallel to enable the cache sub-array in a normal mode and to disable the cache sub-array in the shut-off mode.
Public/Granted literature
- US20070005999A1 Cache leakage shut-off mechanism Public/Granted day:2007-01-04
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