发明授权
US07652921B2 Multi-level non-volatile memory cell with high-VT enhanced BTBT device
有权
具有高VT增强BTBT器件的多级非易失性存储单元
- 专利标题: Multi-level non-volatile memory cell with high-VT enhanced BTBT device
- 专利标题(中): 具有高VT增强BTBT器件的多级非易失性存储单元
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申请号: US12080127申请日: 2008-03-31
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公开(公告)号: US07652921B2公开(公告)日: 2010-01-26
- 发明人: Andrew E. Horch , Bin Wang
- 申请人: Andrew E. Horch , Bin Wang
- 申请人地址: US CA Fremont
- 专利权人: Virage Logic Corporation
- 当前专利权人: Virage Logic Corporation
- 当前专利权人地址: US CA Fremont
- 代理机构: Nixon Peabody LLP
- 代理商 David B. Ritchie
- 主分类号: G11C16/04
- IPC分类号: G11C16/04
摘要:
The present disclosure provides a Non-Volatile Memory (NVM) cell and programming method thereof. The cell can denote at least two logic levels. The cell has a read-transistor with a floating gate, and Band-To-Band-Tunneling device (BTBT device) sharing the floating gate with the read-transistor. The BTBT device is configured as an injection device for injecting a first charge onto the floating gate when the BTBT device is biased with a first gate bias voltage such that the BTBT device is in accumulation, to set at least one of the logic levels. A first electrode is coupled to bias the BTBT device with a first bias voltage that is higher than the first threshold voltage. The first bias voltage is controlled such that the BTBT device is in accumulation during a write operation. The injected amount of charge on the floating gate is determined by the first bias voltage.
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