Invention Grant
- Patent Title: Buffer circuit, amplifier circuit, and test apparatus
- Patent Title (中): 缓冲电路,放大电路和测试装置
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Application No.: US11829939Application Date: 2007-07-29
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Publication No.: US07652466B2Publication Date: 2010-01-26
- Inventor: Hiroki Kimura
- Applicant: Hiroki Kimura
- Applicant Address: JP Tokyo
- Assignee: Advantest Corporation
- Current Assignee: Advantest Corporation
- Current Assignee Address: JP Tokyo
- Agency: Osha • Liang LLP
- Main IPC: G01R1/30
- IPC: G01R1/30 ; H03B1/00

Abstract:
There is provided a buffer circuit that outputs a signal according to an input signal. The buffer circuit includes a first receiving transistor that receives the input signal through its base terminal, a first clamp transistor having polarity same as that of the first receiving transistor, of which an emitter terminal and a collector terminal are connected to corresponding terminals of the first receiving transistor and which receives a first clamp voltage restricting a signal level output from the buffer circuit through its base terminal, and a first current defining section that is commonly provided for the first receiving transistor and the first clamp transistor and defines a total amount of emitter currents flowing into the first receiving transistor and the first clamp transistor. The buffer circuit outputs an output signal according to an emitter voltage of the first receiving transistor.
Public/Granted literature
- US20090027041A1 BUFFER CIRCUIT, AMPLIFIER CIRCUIT, AND TEST APPARATUS Public/Granted day:2009-01-29
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