Invention Grant
- Patent Title: Low power array multiplier
- Patent Title (中): 低功率阵列乘法器
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Application No.: US11083698Application Date: 2005-03-17
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Publication No.: US07546331B2Publication Date: 2009-06-09
- Inventor: Farhad Fuad Islam
- Applicant: Farhad Fuad Islam
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agent Peter M. Kamarchik; Nicholas J. Pauley
- Main IPC: G06F7/53
- IPC: G06F7/53

Abstract:
An array multiplier comprises a partial product array including a plurality of array elements and a final carry propagate adder. Operands smaller than a corresponding dimension of the partial product array are shifted toward the most significant row or column of the array to reduce the number of array elements used to compute the product of the operands. Switching activity in the unused array elements may be reduced by turning off power to the array elements or by padding the shifted operands with zeros in the least significant bits. Additional power saving may be achieved by having bypass lines in the partial product array that bypasses non-essential array elements and by feeding partial sum and carry directly to the final carry propagate adder. Elements of the carry propagate adder may also be bypassed to achieve further power reduction.
Public/Granted literature
- US20060212505A1 Low Power array multiplier Public/Granted day:2006-09-21
Information query
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