发明授权
- 专利标题： Power-on clear circuit
- 专利标题（中）： 上电清零电路
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申请号： US11193470申请日： 2005-08-01
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公开(公告)号： US07498855B2公开(公告)日： 2009-03-03
- 发明人: Hiroyuki Kitajima
- 申请人： Hiroyuki Kitajima
- 申请人地址： JP Kanagawa
- 专利权人： NEC Electronics Corporation
- 当前专利权人： NEC Electronics Corporation
- 当前专利权人地址： JP Kanagawa
- 代理机构： Young & Thompson
- 优先权： JP2004-222678 20040730
- 主分类号： H03K3/02
- IPC分类号： H03K3/02 ; H03L7/00
摘要：
A power-ON-clear circuit has a reset period when the power supply stops temporarily (or instantaneously) and then that power supply is restored. The power-ON-clear circuit 30 of a semiconductor integrated circuit 200 comprises: a capacitor C31 of which one end is connected to the external power-supply voltage Vcc1; an N-channel MOS transistor Q31 of which the drain is connected to the other end of the capacitor C31, the source is connected to the ground potential, and the gate is connected to the external power-supply voltage by way of a resistor R31; and an inverter INV31 that is connected to the connecting point between the capacitor C31 and MOS transistor Q31 in a stage connection, and is connected to the power supply between the internal power-supply voltage Vcc2 and the ground potential.
公开/授权文献
- US20060022725A1 Semiconductor integrated circuit 公开/授权日：2006-02-02
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