Invention Grant
- Patent Title: Method of manufacturing semiconductor integrated circuit device having capacitor element
- Patent Title (中): 具有电容元件的半导体集成电路器件的制造方法
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Application No.: US11172931Application Date: 2005-07-05
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Publication No.: US07323735B2Publication Date: 2008-01-29
- Inventor: Naotaka Hashimoto , Yutaka Hoshino , Shuji Ikeda
- Applicant: Naotaka Hashimoto , Yutaka Hoshino , Shuji Ikeda
- Applicant Address: JP Tokyo
- Assignee: Renesas Technology Corp.
- Current Assignee: Renesas Technology Corp.
- Current Assignee Address: JP Tokyo
- Agency: Antonelli, Terry, Stout & Kraus, LLP.
- Priority: JP7-181513 19950718
- Main IPC: H01L27/108
- IPC: H01L27/108
Abstract:
In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.
Public/Granted literature
- US20050242405A1 Method of manufacturing semiconductor integrated circuit device having capacitor element Public/Granted day:2005-11-03
Information query
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