Invention Grant
- Patent Title: Stacked semiconductor memory device
- Patent Title (中): 堆叠半导体存储器件
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Application No.: US11151213Application Date: 2005-06-14
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Publication No.: US07209376B2Publication Date: 2007-04-24
- Inventor: Hideaki Saito , Yasuhiko Hagihara , Muneo Fukaishi , Masayuki Mizuno , Hiroaki Ikeda , Kayoko Shibata
- Applicant: Hideaki Saito , Yasuhiko Hagihara , Muneo Fukaishi , Masayuki Mizuno , Hiroaki Ikeda , Kayoko Shibata
- Applicant Address: JP Tokyo JP Tokyo
- Assignee: NEC Corporation,Elpida Memory, Inc.
- Current Assignee: NEC Corporation,Elpida Memory, Inc.
- Current Assignee Address: JP Tokyo JP Tokyo
- Agency: Dickstein Shapiro LLP
- Priority: JP2004-191410 20040629
- Main IPC: G11C5/06
- IPC: G11C5/06

Abstract:
A three-dimensional semiconductor memory device having the object of decreasing the interconnection capacitance that necessitates electrical charge and discharge during data transfer and thus decreasing power consumption is provided with: a plurality of memory cell array chips, in which sub-banks that are the divisions of bank memory are organized and arranged to correspond to input/output bits, are stacked on a first semiconductor chip; and interchip interconnections for connecting the memory cell arrays such that corresponding input/output bits of the sub-banks are the same, these interchip interconnections being provided in a number corresponding to the number of input/output bits and passing through the memory cell array chips in the direction of stacking.
Public/Granted literature
- US20050286334A1 Stacked semiconductor memory device Public/Granted day:2005-12-29
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