Invention Grant
- Patent Title: Image processing apparatus
- Patent Title (中): 图像处理装置
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Application No.: US09618537Application Date: 2000-07-18
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Publication No.: US07209260B1Publication Date: 2007-04-24
- Inventor: Hiroshi Tanaka , Yoshiyuki Nakai , Toru Adachi , Keiji Nakamura , Tokiyuki Okano , Kohsuke Harada
- Applicant: Hiroshi Tanaka , Yoshiyuki Nakai , Toru Adachi , Keiji Nakamura , Tokiyuki Okano , Kohsuke Harada
- Applicant Address: JP Osaka
- Assignee: Sharp Kabushiki Kaisha
- Current Assignee: Sharp Kabushiki Kaisha
- Current Assignee Address: JP Osaka
- Agency: Edwards Angell Palmer & Dodge LLP
- Agent David G. Conlin; Mark D. Russett
- Priority: JPP11-204826 19990719
- Main IPC: G06K15/02
- IPC: G06K15/02

Abstract:
The object of the present invention is to use the same FIFO line memory for both enlargement and reduction during variable-magnification processing in the scan direction, allowing reduction in circuit board area, reduction in power consumption, and reduction in cost, and to provide an image processing apparatus that allows variable-magnification processing to be carried out such that the speed of a scanning unit that captures image data during variable-magnification processing in the cross-scan direction is constant. During processing to enlarge an image in the scan direction, image data travels from CCD circuit board, passing through gate b of selector, is written to and read from FIFO memory, and from gate b of selector is written to memory provided at variable magnification unit. At variable magnification unit, image data is read from memory a plurality of times in correspondence to enlargement ratio, changing the magnification of the image data. Furthermore, image data is output through gate a of selector to LSU unit. During processing to reduce an image, image data travels from CCD circuit board, passing through gate a of selector, is input to variable magnification unit where it is subjected to variable-magnification processing, passes through gate a of selector, is written to and read from FIFO memory, passes through gate b of selector, and is output to LSU unit.
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