发明授权
- 专利标题: Voltage reference circuit with reduced power consumption
- 专利标题(中): 电压参考电路,功耗降低
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申请号: US10844320申请日: 2004-05-13
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公开(公告)号: US07042278B2公开(公告)日: 2006-05-09
- 发明人: Heiji Ikoma , Yoshitsugu Inagaki , Koji Oka
- 申请人: Heiji Ikoma , Yoshitsugu Inagaki , Koji Oka
- 申请人地址: JP Osaka
- 专利权人: Matsushita Electric Industrial Co., Ltd.
- 当前专利权人: Matsushita Electric Industrial Co., Ltd.
- 当前专利权人地址: JP Osaka
- 代理机构: Wenderoth, Lind & Ponack, L.L.P.
- 优先权: JP2003-134663 20000513
- 主分类号: G05F3/02
- IPC分类号: G05F3/02
摘要:
A semiconductor integrated circuit is provided with a reference voltage generation circuit for generating a voltage to be a reference, a function circuit that is operated using an output voltage of the reference voltage generation circuit, and a reference voltage stabilization capacitor for stabilizing the output voltage, which is connected to an output terminal of the reference voltage generation circuit. During standby, the function circuit stops operating while the reference voltage generation circuit continues operating to prevent discharging of the reference voltage stabilization capacitor, thereby realizing reduction in power consumption of the function circuit such as an analog circuit as well as high-speed recovery from the standby state to the normal operation state.
公开/授权文献
- US20040245979A1 Semiconductor integrated circuit 公开/授权日:2004-12-09
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