发明授权
- 专利标题: Non-volatile semiconductor memory array and method of reading the same memory array
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申请号: US10317087申请日: 2002-12-12
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公开(公告)号: US07009890B2公开(公告)日: 2006-03-07
- 发明人: Takanori Yamazoe , Hiroshi Yoshigi , Takeo Kanai
- 申请人: Takanori Yamazoe , Hiroshi Yoshigi , Takeo Kanai
- 申请人地址: JP Tokyo JP Kodaira
- 专利权人: Hitachi, Ltd.,Hitachi ULSI Systems Co., Ltd.
- 当前专利权人: Hitachi, Ltd.,Hitachi ULSI Systems Co., Ltd.
- 当前专利权人地址: JP Tokyo JP Kodaira
- 代理机构: Miles & Stockbridge P.C.
- 优先权: JP2002-074049 20020318
- 主分类号: G11C16/00
- IPC分类号: G11C16/00
摘要:
A non-volatile semiconductor memory EEPROM is usually deteriorated depending on the number of times of program and erase operations and application years thereof. A read operation rate of the EEPROM is generally specified to the operation rate considering deterioration of memory and even in the case where the number of times of program and erase operations is rather small and application years are also rather small, the read operation has been conducted at the read operation rate specified considering deterioration of memory. Moreover, when deterioration of memory is advanced exceeding the specified deterioration, the read operation is now disabled in the worst case. In order to overcome such problem, the reference memories are allocated for every erase and program unit block in the EEPROM memory array, the reference memories are also programmed and erased whenever the memories in the block are erased and programmed and the read timing of memory is generated from the read timing of these reference memories. Moreover, the read timing of the reference memories is outputted as an external interface.
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