发明授权
US06877113B2 Break determining circuit for a debugging support unit in a semiconductor integrated circuit
失效
用于半导体集成电路中的调试支持单元的断开确定电路
- 专利标题: Break determining circuit for a debugging support unit in a semiconductor integrated circuit
- 专利标题(中): 用于半导体集成电路中的调试支持单元的断开确定电路
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申请号: US10101777申请日: 2002-03-21
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公开(公告)号: US06877113B2公开(公告)日: 2005-04-05
- 发明人: Toshiaki Saruwatari , Koutarou Tagawa
- 申请人: Toshiaki Saruwatari , Koutarou Tagawa
- 申请人地址: JP Kawasaki
- 专利权人: Fujitsu Limited
- 当前专利权人: Fujitsu Limited
- 当前专利权人地址: JP Kawasaki
- 代理机构: Staas & Halsey LLP
- 优先权: JP2001-108954 20010406
- 主分类号: G06F11/28
- IPC分类号: G06F11/28 ; G06F11/36 ; G06F15/78 ; G06F11/00
摘要:
A semiconductor integrated circuit including a debugging support unit and a buffer memory for temporarily storing trace data, the debugging support unit comprising a break detection member that detects a break signal externally inputted and a break determining member that determines whether the break signal requests to shift to break processing after outputting all the trace data stored in the buffer memory or the break signal requests to shift to the break processing with immediately suspending trace data outputting.
公开/授权文献
- US20020146876A1 Semiconductor integrated circuit 公开/授权日:2002-10-10
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