- Patent Title: Multi-step chemical mechanical polishing of a gate area in a FinFET
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Application No.: US10459495Application Date: 2003-06-12
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Publication No.: US06855607B2Publication Date: 2005-02-15
- Inventor: Krishnashree Achuthan , Shibly S. Ahmed , Haihong Wang , Bin Yu
- Applicant: Krishnashree Achuthan , Shibly S. Ahmed , Haihong Wang , Bin Yu
- Applicant Address: US CA Sunnyvale
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Harrity & Snyder LLP
- Main IPC: C09G1/02
- IPC: C09G1/02 ; H01L21/3105 ; H01L21/321 ; H01L21/336 ; H01L29/423 ; H01L29/49 ; H01L29/786
Abstract:
A method of manufacturing a MOSFET type semiconductor device includes planarizing a gate material layer that is deposited over a channel. The planarization is performed in a multi-step process that includes an initial “rough” planarization and then a “fine” planarization. The slurry used for the finer planarization may include added material that tends to adhere to low areas of the gate material.
Public/Granted literature
- US20040253775A1 MULTI-STEP CHEMICAL MECHANICAL POLISHING OF A GATE AREA IN A FINFET Public/Granted day:2004-12-16
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