Invention Grant
- Patent Title: Method for controlling the quality of a lithographic structuring step
- Patent Title (中): 用于控制光刻结构步骤质量的方法
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Application No.: US10175591Application Date: 2002-06-19
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Publication No.: US06780552B2Publication Date: 2004-08-24
- Inventor: Thorsten Schedel , Jens Zimmermann , Sebastian Schmidt
- Applicant: Thorsten Schedel , Jens Zimmermann , Sebastian Schmidt
- Priority: EP01114670 20010619
- Main IPC: G03F900
- IPC: G03F900

Abstract:
After exposing a semiconductor wafer, quality parameters, for example, the critical dimension, the overlay accuracy, and alignment parameters, etc. are measured in successive inspections and are compared with tolerance range widths that are specified dynamically by calculating the range from measured values of one or more of the other quality parameters. For example, the tolerance range width for the overlay accuracy can be increased for smaller measured critical dimension values of the same structures without affecting the functionality of the integrated circuit. Using a forward mechanism, the tolerance ranges can also be adjusted with the quality parameter measurements from a first layer to the quality parameter tolerance range width of a second layer.
Public/Granted literature
- US20030039905A1 Method for controlling the quality of a lithographic structuring step Public/Granted day:2003-02-27
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