A microprocessor chip and methods for execution by the microprocessor chip. Instruction pipeline circuitry has first and second correct modes for processing at least some instructions. A plurality of flags each correspond to a class of instruction occurring in the instruction pipeline circuitry. Pipeline control circuitry cooperates with the instruction pipeline circuitry, as part of the basic execution cycle of the computer, to maintain the value of the flags to record failures of an attempt to execute in the first mode two mode instructions of the corresponding respective instruction classes, to be triggered by a timer expiry to switch the value of the flags, thereby to switch the instruction pipeline circuitry from one of the processing modes to the other for the corresponding instruction class. The mode switch persists for instructions consecutively executed on behalf of a program that was in execution immediately before the timer expiry, beyond any exception handlers invoked consequent to the timer expiry. As each classified instruction comes up for execution in the instruction pipeline circuitry, the instruction pipeline circuitry executes the instruction in a mode determined, at least in part, by the value of the corresponding flag.