Invention Grant
US06705930B2 System and method for polishing and planarizing semiconductor wafers using reduced surface area polishing pads and variable partial pad-wafer overlapping techniques
有权
使用减小的表面积抛光垫和可变部分焊盘 - 晶片重叠技术来研磨和平坦化半导体晶片的系统和方法
- Patent Title: System and method for polishing and planarizing semiconductor wafers using reduced surface area polishing pads and variable partial pad-wafer overlapping techniques
- Patent Title (中): 使用减小的表面积抛光垫和可变部分焊盘 - 晶片重叠技术来研磨和平坦化半导体晶片的系统和方法
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Application No.: US09754480Application Date: 2001-01-04
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Publication No.: US06705930B2Publication Date: 2004-03-16
- Inventor: John M. Boyd , Yehiel Gotkis , Rod Kistler
- Applicant: John M. Boyd , Yehiel Gotkis , Rod Kistler
- Main IPC: B24B2900
- IPC: B24B2900
Abstract:
A system and method for polishing semiconductor wafers includes a variable partial pad-wafer overlap polisher having a reduced surface area, fixed-abrasive polishing pad and a polisher having a non-abrasive polishing pad for use with an abrasive slurry. The method includes first polishing a wafer with the variable partial pad-wafer overlap polisher and the fixed abrasive polishing pad and then polishing the wafer in a dispersed-abrasive process until a desired wafer thickness is achieved.
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