An analog input signal that is sampled at a predetermined rate is multiplied by a corresponding binary code sequence, i.e. “+1” or “−1” by the multiplier. The output of this multiplier is applied in conjunction with a signal supplied by the negative feed back circuit to the analog integrator. The quantization circuit quantizes the output signal of the analog integrator into N levels and outputs a digital word. This digital word is delayed by a unit time interval by a digital delay circuit and then processed by the above mentioned negative feed back circuit. As a result of this signal magnitude reducing process, the required integrating capacitance can be minimized without risks of saturation effects. Additionally, the output is already in digital form as required by the subsequent system blocks.