发明授权
- 专利标题: Active bias circuit having wilson and widlar configurations
- 专利标题(中): 主动偏置电路具有威尔逊和多边形配置
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申请号: US09794698申请日: 2001-02-26
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公开(公告)号: US06639453B2公开(公告)日: 2003-10-28
- 发明人: Yoshikazu Nishimura , Fuminobu Ono
- 申请人: Yoshikazu Nishimura , Fuminobu Ono
- 优先权: JP2000-052599 20000228
- 主分类号: G05F110
- IPC分类号: G05F110
摘要:
An active bias circuit having a combined configuration of the Wilson and Widlar current source configurations is provided, which makes it possible to set the output bias voltage at approximately 0V even if a reference voltage applied to generate a reference current does not reach 0V. This circuit comprises cascode-connected first and second transistors, cascode-connected third and fourth transistors, and a diode with a specific forward voltage drop generated by a current flowing through the diode itself. The absolute value of the output bias voltage is decreased by the value of the forward voltage drop of the diode compared with the case where the diode is not provided. The diode is provided between the source/emitter of the third transistor and the drain/collector of the fourth transistor, or between the connection point of the third and fourth transistors and the output terminal, or the gates/bases of the first and third transistors.
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