Invention Grant
US06633288B2 Pixel clock PLL frequency and phase optimization in sampling of video signals for high quality image display 有权
像素时钟PLL频率和相位优化采样视频信号,实现高品质图像显示

  • Patent Title: Pixel clock PLL frequency and phase optimization in sampling of video signals for high quality image display
  • Patent Title (中): 像素时钟PLL频率和相位优化采样视频信号,实现高品质图像显示
  • Application No.: US09396016
    Application Date: 1999-09-15
  • Publication No.: US06633288B2
    Publication Date: 2003-10-14
  • Inventor: Sandeep AgarwalArun Johary
  • Applicant: Sandeep AgarwalArun Johary
  • Main IPC: G09G500
  • IPC: G09G500
Pixel clock PLL frequency and phase optimization in sampling of video signals for high quality image display
Abstract:
Pixel clock frequency and optimum sampling phase adjustment is an important requirement in Flat panel display monitors (FPDM) with an analog video interface. This invention proposes a new and more advanced method for frequency and optimum sampling phase determination. It is based on analyzing the content of the image to arrive at an optimum value of phase and frequency by directly optimizing image quality. The method differs from existing methods on two counts. First, no assumptions are needed about the precise value of expected frequency. Second, instead of following a two step approach of first determining frequency and then phase, this invention makes possible a single pass phase-frequency optimization.
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