In a floating point execution unit capable of executing arithmetic operation at high speed, a canceling prediction circuit (60) inputs directly operands before processing of selectors (2 and 3) and predicts a canceling generated in a subtraction result of the operands executed by a subtraction unit (5). The canceling prediction circuit (60) performs the canceling prediction without waiting the completion of carry adjustment of the operands executed by selecting and then executing the selectors (2 and 3). In addition, the prediction error detection circuit (100). Accordingly, when the subtraction result of the subtraction circuit (5) is output through a selector (12), or before the subtraction result is output, the canceling prediction can be executed. Thereby, the left shifter (8) can execute normalization operation for the subtraction result. without waiting, and the error compensation shifter (9) can also execute the compensation operation of the canceling prediction without waiting by using a compensation signal output from the prediction error detection circuit (100).