A clock architecture including a clock source, a multi-phase clock signal generator, a control bus, a number of clock signal lines, and at least one circuit block. The clock source generates a global clock signal, which is then transferred to the multi-phase clock signal generator connected to the clock source. Upon receipt of global clock signal, the multi-phase clock signal generator, which is connected to a control bus, generates clock signals of different phases according to the signals from the control bus. Each of the clock signal branches transfers one of the clock signals of different phases, wherein each of the clock signal branches is individually connected to the circuit block through an electrical switch. Only one switch is at an on state at one time, so that the clock signal of a corresponding phase is transferred to the circuit block. The driving forces applied on the clock buffer connected to the clock source and the clock buffers on the branches are adjustable for reducing clock skew. Alternately, programmable delay buffers can be used for achieving the same goal.