An output power stage which includes a PNP pull-up transistor and an n-channel FET push-down transistor, driven in phase opposition. This fully complementary stage provides an outstandingly improved power handling capability per semiconductor area occupied, together with a large output voltage swing, but does not require the use of externally connected discrete boot-strap components. The bipolar pull-up transistor can optionally be driven through an FET auxiliary stage, to minimize the power requirements of the preceding signal amplification stage.