Invention Grant
- Patent Title: Method and system for identifying failure point
- Patent Title (中): 识别故障点的方法和系统
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Application No.: US902209Application Date: 1997-07-29
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Publication No.: US5944847APublication Date: 1999-08-31
- Inventor: Masaru Sanada
- Applicant: Masaru Sanada
- Applicant Address: JPX Tokyo
- Assignee: Tokyo, Japan
- Current Assignee: Tokyo, Japan
- Current Assignee Address: JPX Tokyo
- Priority: JPX8-216130 19960729
- Main IPC: G01R31/317
- IPC: G01R31/317 ; G01R31/28 ; G01R31/30 ; G06F17/50
Abstract:
A failure point identifying method applicable to various defects and capable of promptly identifying a defect point. An LSI tester 4 sequentially impresses test vectors stored in a test vector file 1 across input terminals of a loaded LSI 5 to measure an Iddq value. A test vector number of a test vector which produced an abnormal Iddq value is delivered to a faulty block extractor 2. The faulty block extractor 2 performs logic simulation to find the input logic of each block of the LSI 5 when each test vector stored in the test vector file 1 is entered to the input terminals of the LSI 5. Moreover, a dump list associating each test vector number with the input logic is prepared from block to block. The faulty block is then identified based on the dump list of each block and the test vector number deliver from the LSI tester.
Public/Granted literature
- US5285415A Data counting memory card and reader Public/Granted day:1994-02-08
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