A system (10) for transmitting a synchronous stream of data is set forth. The system (10) includes a universal asynchronous transmitter/receiver (30) includes a circuit for asynchronously transmitting a data character; a timing circuit for generating a signal (255, 260) upon completion of the asynchronous transmission of the data character; and an output line (140, 145) controllable to go to a data state independent of the data states of the bits of the data character. The system further includes a central processing circuit (15, 20, 25) that is responsive to the timing circuit of the UART (30). The central processing circuit (15, 20, 25) controls the output line (140, 145) of the UART (30) to go to a series of data states corresponding to individual bits of the synchronous data stream. The period of the individual bits corresponds to the signal generated by the timing circuit.