An implantable cardiac stimulation device that has automatic functions in each of two different sets of microprocessor operating code. Following implantation, a first mode of operation executes a first set of operating code, stored primarily in RAM, and performs software error detection. Upon detection of an error, the microprocessor is caused to enter a second (backup) mode of operation, where it executes a second set of operating code, which is retained in read-only memory (ROM). Thus, in the unlikely event of error detection, the implantable device is still fully functional in its second mode to provide automaticity, e.g., to select therapies for different heart condition and provide rate-responsive pacing that tracks physiological requirements. If an error is detected in the second mode, than a third mode of operation (e.g., fixed-rate VVI pacing) is enabled.