Invention Grant
- Patent Title: Method of manufacturing a bonded semiconductor substrate and a dielectric isolated bipolar transistor
- Patent Title (中): 制造键合半导体衬底和介质隔离双极晶体管的方法
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Application No.: US340361Application Date: 1994-11-14
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Publication No.: US5476813APublication Date: 1995-12-19
- Inventor: Hiroshi Naruse
- Applicant: Hiroshi Naruse
- Applicant Address: JPX Kawasaki
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JPX Kawasaki
- Priority: JPX5-284780 19931115
- Main IPC: H01L29/73
- IPC: H01L29/73 ; H01L21/02 ; H01L21/18 ; H01L21/331 ; H01L21/762 ; H01L21/84 ; H01L27/12 ; H01L21/20
Abstract:
In a method of manufacturing a bonded semiconductor substrate, a SiGe mixed crystal layer, a silicon layer containing N-type impurities, a SiGe mixed crystal layer containing N-type impurities of high concentration, and a silicon layer containing N-type impurities of high concentration are formed in this order on a top surface of a silicon substrate by an epitaxial growth process to form a first semiconductor substrate. A silicon oxide film is formed on a surface of a silicon substrate to form a second semiconductor substrate. The first and second semiconductor substrates are bonded to each other by heat treatment, with their top surfaces contacting each other. The first semiconductor substrate is etched from the back surface thereof until the SiGe mixed crystal layer is exposed, and the SiGe mixed crystal layer is etched until the silicon layer containing N-type impurities is exposed. This method prevents the thickness of the element forming layer from varying.
Public/Granted literature
- US4451031A Signature machines Public/Granted day:1984-05-29
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