In an information processing system for use in detecting an error in a main memory (11) comprising a plurality of memory units (111 to 118) and a common control section (19), an error detection signal and an error address are sent from a request source processor (15) to a diagnostic address generator (31) when an error is detected on an access operation of the request source processor. On diagnostic access operations, the diagnostic address generator successively produces a plurality of diagnostic addresses including the error address to receive diagnostic replies, each of which comprises a reply code. When an error of the main memory is indicated by the reply code, an error detection controller (32) discriminates the diagnostic address on occurrence of the error in the diagnostic operations to disconnect the memory unit or units from the main memory by the use of a memory restructuring circuit (36). All of the memory units are disconnected when a malfunction of the common control section is discriminated by the error detection controller.