A multiprocessor system is disclosed for controlling a cycle of operation of a machine. The cycle of operation of the machine is governed by a first set of devices and is monitored by a second set of devices. The multiprocessor system includes a logic processor unit containing a first program of logic instructions defining the cycle of operation of the machine. A bus and associated circuits are connected between the logic processor and the devices on the machine. The logic processor is responsive to the second set of devices and makes logic decisions in a continuous and cyclic manner to control the operation of the first devices thereby causing the cycle of operation of the machine to conform with the first program. The multiprocessor system further includes one or more independent data processors which are connected to the bus and operate asynchronously with the logic processor. The data processors respond to output signals from the logic processor which select preprogrammed sets of arithmetic instructions. The data processors execute the selected sets of arithmetic instructions and produce control signals which are accepted by the logic processor at the appropriate time in its own cycle of operation.