A circuit to be used with a transistorized logic memory which will cause the memory to be retentive when input power to the memory is interrupted and may be used in complex logic circuits, e.g., counters, shift registers, etc., which operate at high rates of speed. The retentive memory function is achieved by supplying inputs to the memory through a bistable state reed relay which causes the bistable state of the memory to correspond to the bistable state of the reed relay when power to the memory is initiated and supplying the outputs of the memory to the inputs of the reed relay which causes the bistable state of the reed relay to correspond to the bistable state of the memory when power to the memory is interrupted. The circuit is also arranged to prevent operation of the reed relay when the voltage of the direct current power source for the logic system is normal.