Invention Application
- Patent Title: MANUFACTURING METHOD OF ELECTRONIC PACKAGE AND ELECTRONIC PACKAGE
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Application No.: US18476279Application Date: 2023-09-27
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Publication No.: US20240421124A1Publication Date: 2024-12-19
- Inventor: Wen-Yuan Chang , Wei-Cheng Chen , Chen-Yueh Kung
- Applicant: VIA Technologies, Inc.
- Applicant Address: TW New Taipei City
- Assignee: VIA Technologies, Inc.
- Current Assignee: VIA Technologies, Inc.
- Current Assignee Address: TW New Taipei City
- Priority: TW112122519 20230616
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/00 ; H01L23/498 ; H01L23/538

Abstract:
A manufacturing method of an electronic package includes the following steps. Multiple chips and a base dielectric layer are provided. A back surface of each chip is fixed to a back surface temporary carrier via a back surface temporary bonding layer. A base dielectric layer surrounds each chip and covers the back surface temporary bonding layer. A material of the base dielectric layer includes a silicate composite material. At least one bridge element is installed on the adjacent chips. An intermediate dielectric layer covering the base dielectric layer, the chips, and the bridge element is formed. Multiple intermediate conductive vias and a redistribution structure are respectively formed on the chips and the intermediate dielectric layer. Multiple conductive bumps are formed on the redistribution structure. The back surface temporary bonding layer and the back surface temporary carrier are removed. An electronic package produced by the manufacturing method is also provided.
Information query
IPC分类: