- 专利标题: MEMORY MANAGEMENT HOLDING LATCH PLACEMENT AND CONTROL SIGNAL GENERATION
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申请号: US18607152申请日: 2024-03-15
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公开(公告)号: US20240362114A1公开(公告)日: 2024-10-31
- 发明人: Jaeil Kim , Donald M. Morgan , Alan J. Wilson
- 申请人: Micron Technology, Inc.
- 申请人地址: US ID Boise
- 专利权人: Micron Technology, Inc.
- 当前专利权人: Micron Technology, Inc.
- 当前专利权人地址: US ID Boise
- 主分类号: G06F11/10
- IPC分类号: G06F11/10
摘要:
A system for providing memory management holding latch placement and control signal generation is disclosed. The system performs memory management operations on a memory device to reduce memory cell wear and tear and to balance use of the memory cells of the memory device. The system separates memory management read operations from memory management write operations by utilizing a holding register that stores data from a source memory cell prior to transfer to a target memory cell. When a memory management read operation is initiated, data and error correction parity bits from the source memory cell are provided to a circuit including the holding register. The data and parity bits are analyzed for errors and the errors are corrected prior to storing the data and parity bits into the holding register. The data and associated parity bits are then transferred from the holding register to the target memory cell.
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