发明公开
- 专利标题: LOW-STRESS PASSIVATION LAYER
-
申请号: US18672485申请日: 2024-05-23
-
公开(公告)号: US20240312885A1公开(公告)日: 2024-09-19
- 发明人: Hsiang-Ku Shen , Chun-Li Lin , Dian-Hau Chen
- 申请人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 申请人地址: TW Hsinchu
- 专利权人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人地址: TW Hsinchu
- 分案原申请号: US16656617 2019.10.18
- 主分类号: H01L23/498
- IPC分类号: H01L23/498 ; H01L21/02 ; H01L21/48 ; H01L23/532
摘要:
Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a redistribution layer including a first conductive feature and a second conductive feature, a first contact feature disposed over and electrically coupled to the first conductive feature, a second contact feature disposed over and electrically coupled to the second conductive feature, and a passivation feature extending from between the first conductive feature and the second conductive feature between the first contact feature and the second contact feature. The passivation feature includes a dielectric feature and a dielectric layer. The dielectric layer is disposed on a planar top surface of the dielectric feature and a composition of the dielectric feature is different from a composition of the dielectric layer.
信息查询
IPC分类: