The present disclosure describes a memory device comprising memory cells at cross points of access lines of a memory array, and a two-transistor driver comprising a P-type transistor and a N-type transistor connected to the P-type transistor, the two-transistor driver being configured to drive a first one of the access lines to a read/program voltage through the two-transistor driver, during a PULSE phase and drive a second one of the access lines physically adjacent to the first one of the access lines to a shielding voltage through the two-transistor driver, during the PULSE phase.