Invention Publication
- Patent Title: EMBEDDED DIE PACKAGING FOR POWER SEMICONDUCTOR DEVICES FOR IMPROVED SOLDER RELIABILITY
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Application No.: US18522911Application Date: 2023-11-29
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Publication No.: US20240213127A1Publication Date: 2024-06-27
- Inventor: Abhinandan DIXIT , An-Sheng CHENG , Di CHEN , Hossein MOUSAVIAN
- Applicant: GAN SYSTEMS INC.
- Applicant Address: CA OTTAWA
- Assignee: GAN SYSTEMS INC.
- Current Assignee: GAN SYSTEMS INC.
- Current Assignee Address: CA OTTAWA
- Main IPC: H01L23/495
- IPC: H01L23/495 ; H01L21/8234 ; H01L23/00 ; H01L25/065

Abstract:
A laminated embedded die package for a power semiconductor device, wherein a laminated body comprises a layup of a plurality of electrically conductive layers and dielectric layers. The die may be mounted in thermal contact with a leadframe. Electrical connections between contact areas of the die, external contact pads of the package and internal conductive layers are made by electrically conductive vias or microvias, formed by laser drilling of vias through the dielectric layers, which are then filled with conductive metal. A plurality of unfilled half-vias are arranged around edges of the laminated body adjacent external contact pads. Half-vias are formed by laser or mechanical drilling along scribe lines before singulation of packages. Surface plating of the half-vias comprises a solder wettable material. The half-vias are unfilled to form a wettable flank which allows for lateral wicking of solder during surface mounting, to facilitate optical inspection of solder reliability.
Information query
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