A first backside power rail directly below and connected to a first source-drain epitaxy region of a positive field effect transistor (p-FET) region via a first backside contact vertically aligned with the first source-drain epitaxy region, the first backside power rail directly contacts an upper horizontal surface of the first backside contact and the first backside power rail directly contacts a vertical side surface of the first backside contact. Forming a first backside power rail directly below and connected to a first source-drain epitaxy region of a positive field effect transistor (p-FET) region via a first backside contact vertically aligned with the first source-drain epitaxy region, where the first backside power rail directly contacts an upper horizontal surface of the first backside contact and the first backside power rail directly contacts a vertical side surface of the first backside contact.