Invention Publication
- Patent Title: PAGE RETIREMENT TECHNIQUES FOR MULTI-PAGE DRAM FAULTS
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Application No.: US17977001Application Date: 2022-10-31
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Publication No.: US20240143440A1Publication Date: 2024-05-02
- Inventor: Sudhanva Gurumurthi , Vilas Sridharan , Majed Valad Beigi
- Applicant: ADVANCED MICRO DEVICES, INC.
- Applicant Address: US CA Santa Clara
- Assignee: ADVANCED MICRO DEVICES, INC.
- Current Assignee: ADVANCED MICRO DEVICES, INC.
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06F11/10
- IPC: G06F11/10 ; G06F11/07 ; G06F12/1027

Abstract:
A processing system employs techniques for enhancing dynamic random access memory (DRAM) page retirement to facilitate identification and retirement of pages affected by multi-page DRAM faults. In response to detecting an uncorrectable error at a first page of DRAM, the processing system identifies a second page of the DRAM for potential retirement based on one or more of physical proximity to the first page, inclusion in a range of addresses stored at a fault map that tracks addresses of DRAM pages having detected faults, and predicting a set of pages to check for faults based on misses at a translation lookaside buffer (TLB).
Public/Granted literature
- US12216539B2 Page retirement techniques for multi-page DRAM faults Public/Granted day:2025-02-04
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