发明公开
- 专利标题： PROCESSOR BINDING TECHNIQUE
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申请号： US18207077申请日： 2023-06-07
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公开(公告)号： US20240069969A1公开(公告)日： 2024-02-29
- 发明人: Raghav Hrishikeshan Mukundan , Suryanarayan Ramamurthy , Sanjay Chatterjee , Sukesh Roy
- 申请人： NVIDIA Corporation
- 申请人地址： US CA Santa Clara
- 专利权人： NVIDIA Corporation
- 当前专利权人： NVIDIA Corporation
- 当前专利权人地址： US CA Santa Clara
- 主分类号： G06F9/50
- IPC分类号： G06F9/50
摘要：
Apparatuses, systems, and techniques to perform software workloads. In at least one embodiment, one or more circuits of a processor cause a programming interface to select a subset of one or more processors of a non-uniform memory access (NUMA) node to perform a software workload.
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