Invention Application
- Patent Title: PERMUTATION CIPHER ENCRYPTION FOR PROCESSOR-ACCELERATOR MEMORY MAPPED INPUT/OUTPUT COMMUNICATION
-
Application No.: US18068663Application Date: 2022-12-20
-
Publication No.: US20230117518A1Publication Date: 2023-04-20
- Inventor: Santosh Ghosh , Luis Kida , Reshma Lal
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H04L9/08
- IPC: H04L9/08 ; H04L9/06

Abstract:
Technologies for secure data transfer of MMIO data between a processor and an accelerator. A MIMO security engine includes a first permutation cipher pipeline to defuse a count and a key into a permutation state; a first exclusive-OR (XOR) to generate ciphertext data from 64-bits of the new permutation state; and plaintext data; a concatenator to concatenate the plaintext data and additional authenticated data (AAD) to produce a concatenation result; a second XOR to generate an XOR result from the concatenation result and the latest permutation state; and a second permutation pipeline to generate an authentication tag of the XOR result and the key.
Public/Granted literature
- US11838411B2 Permutation cipher encryption for processor-accelerator memory mapped input/output communication Public/Granted day:2023-12-05
Information query