发明申请
- 专利标题: Off-Chip Memory Backed Reliable Transport Connection Cache Hardware Architecture
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申请号: US17553387申请日: 2021-12-16
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公开(公告)号: US20230062889A1公开(公告)日: 2023-03-02
- 发明人: Weihuang Wang , Srinivas Vaduvatha , Xiaoming Wang , Gurushankar Rajamani , Abhishek Agarwal , Jiazhen Zheng , Prashant Chandra
- 申请人: Google LLC
- 申请人地址: US CA Mountain View
- 专利权人: Google LLC
- 当前专利权人: Google LLC
- 当前专利权人地址: US CA Mountain View
- 主分类号: H04L67/568
- IPC分类号: H04L67/568 ; H04L49/00 ; H04L69/326 ; G06F16/2455
摘要:
An application specific integrated circuit (ASIC) is provided for reliable transport of packets. The network interface card may include a reliable transport accelerator (RTA). The RTA may include a cache lookup database. The RTA may be configured to determine, from a received data packet, a connection identifier and query the cache lookup database for a cache entry corresponding to a connection context having the connection identifier. In response to the query, the RTA may receive a cache hit or a cache miss.
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