Systems, methods, and apparatus related to memory devices (e.g., storage class memory). In one approach, a memory device has a memory array including memory cells arranged as differential memory cell pairs, with each pair storing a single logical bit. The memory device has a controller that receives a command from a host to initiate a read operation. The memory cell pair is selected using bitlines and a common wordline. A partition of the memory array is accessed to read the data stored by the memory cell pair, and then store the read data in a latch for sending to the host. In response to accessing the partition, a counter is incremented. The controller statistically determines whether to perform a refresh operation for the partition based on comparing the current value of the counter to a value previously generated by a random number generator.