- 专利标题： Analog Multiplexer Circuit and Analog-Digital Conversion System
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申请号： US17768168申请日： 2019-10-23
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公开(公告)号： US20230336185A1公开(公告)日： 2023-10-19
- 发明人: Munehiko Nagatani , Teruo Jo , Hiroshi Yamazaki , Hideyuki Nosaka
- 申请人： Nippon Telegraph and Telephone Corporation
- 申请人地址： JP Tokyo
- 专利权人： Nippon Telegraph and Telephone Corporation
- 当前专利权人： Nippon Telegraph and Telephone Corporation
- 当前专利权人地址： JP Tokyo
- 国际申请： PCT/JP2019/041475 2019.10.23
- 进入国家日期： 2022-04-11
- 主分类号： H03M1/12
- IPC分类号： H03M1/12 ; H03K17/693
摘要：
An analog demultiplexer circuit includes a clock distribution circuit that outputs clock signals (CK1P and CK1N) and clock signals (CK2P and CK2N) complementary thereto, a track-and-hold circuit that holds analog input signals (VINP and VINN) in synchronization with the clock signals (CK1P and CK1N), and a track-and-hold circuit that holds the analog input signals (VINP and VINN) in synchronization with the clock signals (CK2P and CK2N).
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