- 专利标题: Transposing Memory Layout of Weights in Deep Neural Networks (DNNs)
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申请号: US17937592申请日: 2022-10-03
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公开(公告)号: US20230229910A1公开(公告)日: 2023-07-20
- 发明人: Kevin Brady , Sudheendra Kadri , Niall Hanrahan
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 主分类号: G06N3/08
- IPC分类号: G06N3/08 ; G06N3/04 ; G06F13/28
摘要:
A compute block includes a DMA engine that reads data from an external memory and write the data into a local memory of the compute block. An MAC array in the compute block may use the data to perform convolutions. The external memory may store weights of one or more filters in a memory layout that comprises a sequence of sections for each filter. Each section may correspond to a channel of the filter and may store all the weights in the channel. The DMA engine may convert the memory layout to a different memory layout, which includes a sequence of new sections for each filter. Each new section may include a weight vector that includes a sequence of weights, each of which is from a different channel. The DMA engine may also compress the weights, e.g., by removing zero valued weights, before the conversion of the memory layout.
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