Invention Application
- Patent Title: MEMORY DEVICE CURRENT LIMITER
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Application No.: US17816005Application Date: 2022-07-29
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Publication No.: US20220366980A1Publication Date: 2022-11-17
- Inventor: Chung-Cheng Chou , Tien-Yen Wang
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Main IPC: G11C13/00
- IPC: G11C13/00

Abstract:
A memory device includes a memory array including a plurality of memory cells arranged in rows and columns. A closed loop bias generator is configured to output a column select signal to the memory array. A current limiter receives an output of the closed loop bias generator. The current limiter is coupled to a plurality of the columns of the memory array.
Public/Granted literature
- US11948635B2 Memory device current limiter Public/Granted day:2024-04-02
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