- 专利标题: FLOATING POINT MULTIPLY-ACCUMULATE UNIT FOR DEEP LEARNING
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申请号: US17688131申请日: 2022-03-07
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公开(公告)号: US20220188075A1公开(公告)日: 2022-06-16
- 发明人: Arnab Raha , Mark A. Anders , Raymond Jit-Hung Sung , Debabrata Mohapatra , Deepak Abraham Mathaikutty , Ram K. Krishnamurthy , Himanshu Kaul
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 主分类号: G06F7/544
- IPC分类号: G06F7/544 ; G06F7/483 ; G06N3/08
摘要:
A FPMAC operation has two operands: an input operand and a weight operand. The operands may have a format of FP16, BF16, or INT8. Each operand is split into two portions. The two portions are stored in separate storage units. Then operands are transferred to register files of a PE, with each register file storing bits of an operand sequentially. The PE performs the FPMAC operation based on the operands. The PE may include an FPMAC unit configured to compute an individual partial sum of the PE. The PE may also include an FP adder to accumulate the individual partial sum with other data, such as an output from another PE or an output form another PE array. The FP adder may be fused with the FPMAC unit in a single circuit that can do speculative alignment and has separate critical paths for alignment and normalization.
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