发明申请
- 专利标题： Method Of Forming Split Gate Memory Cells With Thinned Side Edge Tunnel Oxide
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申请号： US16910022申请日： 2020-06-23
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公开(公告)号： US20210399127A1公开(公告)日： 2021-12-23
- 发明人: Jinho Kim , Elizabeth Cuevas , Yuri Tkachev , Parviz Ghazavi , Bernard Bertello , Gilles Festes , Bruno Villard , Catherine Decobert , Nhan Do , Jean Francois Thiery
- 申请人： Silicon Storage Technology, Inc.
- 申请人地址： US CA San Jose
- 专利权人： Silicon Storage Technology, Inc.
- 当前专利权人： Silicon Storage Technology, Inc.
- 当前专利权人地址： US CA San Jose
- 主分类号： H01L29/788
- IPC分类号： H01L29/788 ; H01L29/66 ; H01L27/11517
摘要：
A memory device includes a semiconductor substrate with memory cell and logic regions. A floating gate is disposed over the memory cell region and has an upper surface terminating in opposing front and back edges and opposing first and second side edges. An oxide layer has a first portion extending along the logic region and a first thickness, a second portion extending along the memory cell region and has the first thickness, and a third portion extending along the front edge with the first thickness and extending along a tunnel region portion of the first side edge with a second thickness less than the first thickness. A control gate has a first portion disposed on the oxide layer second portion and a second portion vertically over the front edge and the tunnel region portion of the first side edge. A logic gate is disposed on the oxide layer first portion.
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