THREE-LEVEL PULSE WIDTH MODULATION TECHNIQUE FOR REDUCING SEMICONDUCTOR SHORT CIRCUIT CONDUCTION LOSS
摘要:
A converter implementing a dual-reference three-level pulse width modulation (PWM) technique for constraining a midpoint duty cycle is provided. The converter includes a phase leg that includes upper, mid-upper, mid-lower, and lower switches. The upper, mid-upper, mid-lower, and lower switches are connected in series between direct current (DC) positive and negative leads, with an alternating current (AC) output lead connected at a junction of the mid-upper and mid-lower switches. The phase leg includes a first clamping diode connected to the junction of the switch and mid-upper switches and connected to a DC midpoint lead and a second clamping diode connected between the DC midpoint lead and connected to the junction of the mid-lower and lower switches. The converter is electrically coupled to and operatively associated with a controller to receive control signals to drive the converter to constrain the midpoint duty cycle between the DC midpoint and AC output leads.
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