Invention Application
- Patent Title: INTERCONNECT METAL LAYOUT FOR INTEGRATED CIRCUIT
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Application No.: US15457640Application Date: 2017-03-13
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Publication No.: US20180151567A1Publication Date: 2018-05-31
- Inventor: Wei-Cheng LIN , Kam-Tou SIO , Jiann-Tyng TZENG , Charles Chew-Yuen YOUNG
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW HSINCHU
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW HSINCHU
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L23/528 ; H01L23/522 ; H01L27/02 ; H01L21/8238 ; H01L21/768

Abstract:
A semiconductor device includes an active region comprising a source/drain region and a plurality of poly strips spaced apart and arranged along a first direction crossing over the active region. The first direction is substantially perpendicular to a lengthwise direction of the active region. A first metal pattern is disposed on the poly strips and arranged along the first direction. A plurality of first interconnect plugs is interposed in between the poly strips and the first metal pattern and in between the active region and the first metal pattern. A position of the first interconnect plugs being variable along the first direction.
Public/Granted literature
- US10157922B2 Interconnect metal layout for integrated circuit Public/Granted day:2018-12-18
Information query
IPC分类: