Invention Application
- Patent Title: High-Speed Receiver Architecture
- Patent Title (中): 高速接收机架构
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Application No.: US14480085Application Date: 2014-09-08
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Publication No.: US20150098710A1Publication Date: 2015-04-09
- Inventor: Oscar Ernesto Agazzi , Diego Ernesto Crivelli , Hugo Santiago Carrer , Mario Rafael Hueda , German Cesar Augusto Luna , Carl Grace
- Applicant: ClariPhy Communications. Inc.
- Main IPC: H04B10/40
- IPC: H04B10/40
Abstract:
A receiver (e.g., for a 10G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.
Public/Granted literature
- US09531475B2 High-speed receiver architecture Public/Granted day:2016-12-27
Information query
