发明申请
US20140369400A1 Low Power Oversampling With Reduced-Architecture Delay Locked Loop
审中-公开
具有减少架构延迟锁定环路的低功耗过采样
- 专利标题： Low Power Oversampling With Reduced-Architecture Delay Locked Loop
- 专利标题（中）： 具有减少架构延迟锁定环路的低功耗过采样
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申请号： US14326657申请日： 2014-07-09
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公开(公告)号： US20140369400A1公开(公告)日： 2014-12-18
- 发明人: Wei-Lien Yang
- 申请人： Intel Corporation
- 主分类号： H04L7/00
- IPC分类号： H04L7/00 ; H04L25/49
摘要：
In one embodiment, an apparatus including a phase detector unit to determine a phase difference between an inverted reference clock signal and a feedback clock signal. The apparatus further includes a controller unit to generate a delay signal based on the phase difference. The apparatus further includes a set of voltage-controlled delay lines to generate phase outputs based on the delay signal, where the phase outputs are provided by the apparatus to a clock generator unit to generate an oversampled clock signal for data recovery by a receiver.
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