Invention Application
US20140353846A1 Semiconductor Device and Method of Forming Interconnect Structure and Mounting Semiconductor Die in Recessed Encapsulant
有权
半导体器件和在嵌入式封装中形成互连结构和安装半导体管芯的方法
- Patent Title: Semiconductor Device and Method of Forming Interconnect Structure and Mounting Semiconductor Die in Recessed Encapsulant
- Patent Title (中): 半导体器件和在嵌入式封装中形成互连结构和安装半导体管芯的方法
-
Application No.: US14462347Application Date: 2014-08-18
-
Publication No.: US20140353846A1Publication Date: 2014-12-04
- Inventor: Linda Pei Ee Chua , Byung Tai Do , Reza A. Pagaila
- Applicant: STATS ChipPAC, Ltd.
- Applicant Address: SG Singapore
- Assignee: STATS CHIPPAC, LTD.
- Current Assignee: STATS CHIPPAC, LTD.
- Current Assignee Address: SG Singapore
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L25/065 ; H01L21/768 ; H01L25/00

Abstract:
A semiconductor device has conductive pillars formed over a carrier. A first semiconductor die is mounted over the carrier between the conductive pillars. An encapsulant is deposited over the first semiconductor die and carrier and around the conductive pillars. A recess is formed in a first surface of the encapsulant over the first semiconductor die. The recess has sloped or stepped sides. A first interconnect structure is formed over the first surface of the encapsulant. The first interconnect structure follows a contour of the recess in the encapsulant. The carrier is removed. A second interconnect structure is formed over a second surface of the encapsulant and first semiconductor die. The first and second interconnect structures are electrically connected to the conductive pillars. A second semiconductor die is mounted in the recess. A third semiconductor die is mounted over the recess and second semiconductor die.
Public/Granted literature
Information query
IPC分类: